1. Field of the Invention
This invention pertains in general to a semiconductor device, and, more particularly, to a substrate-biased silicon diode and a method for making the same.
2. Background of the Invention
A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is provided to the IC. The high current may be built-up from a variety of sources, such as the human body. Many schemes have been implemented to protect an IC from an ESD event. A common protection scheme is using a parasitic transistor associated with an n-type metal-oxide semiconductor (MOS) with the source coupled to ground and the drain connected to the pin to be protected from an ESD event.
Diodes or diode-coupled transistors have been used for ESD protection in radio-frequency (RF) applications. In a RF IC, an on-chip ESD circuit should ideally provide robust-ESD protection, while exhibiting minimum parasitic input capacitance and low voltage-dependency. In deep-submicron complementary metal-oxide semiconductor (CMOS) process technology with shallow-trench isolations (STIs), a diode has been used for ESD protection and is generally formed contiguous with either an N+ or P+ diffusion region in a semiconductor substrate. FIG. 1A shows a cross-sectional view of a known diode ESD protection structure formed in an IC. Referring to FIG. 1A, a P+ diffusion region is bound by STIs on either side, and therefore the diode formed by the STI is also known as an STI-bound diode. The STI-bound diode exhibits a bottom capacitance, Cbottom. However, an STI-bound diode has been found to have significant leakage current due to an interference between a silicide layer (not shown) of the P+ diffusion region and the STIs around the P+ region.
FIG. 1B shows a cross-sectional view of another known diode ESD protection structure, known as a polysilicon-bound diode, introduced to address the leakage current problem with an STI-bound diode. The P+ diffusion region in a polysilicon-bound diode is now defined by a polysilicon gate, and therefore the leakage current from the edges of STIs is eliminated. However, the total parasitic capacitance of the polysilicon-bound diode is larger than that of the STI-bound diode because of the addition of the sidewall junction capacitance of the P+ diffusion region.
FIG. 2 is a circuit diagram showing a known ESD protection scheme using dual diodes. Referring to FIG. 2, the combination of the dual-diode structures and VDD-to-VSS ESD clamp circuit provides a path for an ESD current 2 to discharge, instead of through the internal circuits. When ESD current 2 is provided to a signal pad PAD1, and with a signal pad PAD2 relatively grounded, ESD current 2 is conducted to VDD through Dp1. ESD current 2 is discharged to VSS through the VDD-to-VSS ESD clamp circuit and flows out of the IC from Dn2 to PAD2. Diode Dp1 has a capacitance of Cp1 and diode Dn1 has a capacitance of Cn1. The total input capacitance Cin of the circuit shown in FIG. 2 primarily comes from the parasitic junction capacitance of diodes, and is calculated as follows:Cin=Cp1+Cn1
wherein Cp1 and Cn1 are parasitic junction capacitances of diodes Dp1 and Dn1, respectively.
FIG. 3 is plot showing the relationship between a pad voltage and parasitic input capacitance of the circuit shown in FIG. 2. Referring to FIG. 3, when the voltage on the pad increases, the parasitic junction capacitance of Dp1 increases and the parasitic junction capacitance of Dn1 decreases. Therefore, the total input parasitic capacitance Cin is nearly constant. This characteristic is important in RF applications. However, the total parasitic capacitance of a polysilicon-bound diode, as compared to an STI-bound diode, is increased because of the addition of a sidewall capacitance, Csidewall, as shown in FIG. 1B.